Semiconductor memories can be classified as volatile (where stored information is lost upon power removal) and non-volatile (where stored information is maintained after power removal, and which can be accurately retrieved upon subsequent power-up).
Probably the most common type of semiconductor memory is based upon the well-known latch, or flip-flop, configuration having a pair of cross-coupled inverter transistors (the driver transistors of the latch) together with accompanying loads.
It is known to make MOS latch circuits with non-volatile characteristics: one such type of circuit is based upon the use of FATMOS transistors. FATMOS non-volatile latch circuits are described and claimed in U.S. Pat. No. 4,132,904 and U.K. Specification No. 2,000,407.
The FATMOS is basically a control gate plus floating gate MOS transistor with a portion of the floating gate lying close to the semiconductor substrate. When the source and drain connections are connected to an appropriate potential (one positive relative to the other) and a suitable potential of a first magnitude applied to the control gate, the transistor conducts. Upon removal of the control gate potential, conduction ceases. If a potential of a second and higher magnitude is applied to the control gate with the drain at zero voltage, the transistor again conducts, but in addition electric charges tunnel between the floating gate and the transistor substrate through the portion of the floating gate closest to the substrate. This charge remains on the floating gate even when the control gate potential is removed and increases the switching threshold of the device. This charge on the floating gate enables the transistor to be employed in a non-volatile memory, as described in U.K. Specification No. 2,000,407. The switching threshold of the FATMOS is returned to its original level by applying between the control gate and drain a potential of approximately the second and higher potential, but of opposite sign.
In a typical example of an N-channel enhancement-type FATMOS, the area of the floating gate closest to the substrate overlies the drain of the transistor, although this is not essential and the area closest to the substrate can be to elsewhere on the transistor. In normal, non-volatile operation, a voltage of typically +5 to +7 volts is applied to the control gate. To operate the device as a non-volatile transistor, a voltage of typically +8 to +15 volts is applied to the control gate.
It is also known to construct latch circuits from the different known types of MOS transistors notably PMOS, CMOS and NMOS. In terms of the development of MOS technology PMOS latches were initially popular since their production is the most straightforward. CMOS latches (with complementary P-channel and N-channel transistors) have also become popular mainly because of their low current consumption. NMOS latches have proved more difficult to produce on a commercial scale until relatively recently, although it has been recognised that they would have substantial advantages over other types, especially in their speed of operation--which is often of paramount consideration in memory circuits.
The above-identified U.S. and U.K. patent specifications do disclose NMOS latches with non-volatility characteristics provided by the use of FATMOS transistors. In this regard reference is directed to FIGS. 8 to 10 of said patent specifications. It is also stated in the said patent specifications that when purely N-channel or P-channel technology is employed in the latches, the variable threshold transistors (i.e. the FATMOS's) will always be the drivers. In practice, it has been found that purely NMOS latches with FATMOS driver transistors must be provided with additional NMOS transistors in series and possibly also in parallel. The reason for this resides in the fact that FATMOS transistors have a wide range of threshold voltages and cannot sometimes accurately maintain the correct logic state of the latch. During normal read operations the phenomenon of "knockover" can occur wherein, rather than the latch dictating its logic state out to the data line(s), the opposite occurs. In such a case, the data line(s) can dictate their electrical states to the latch so that the latch may change state unpredictably. This phenomenon (essentially a capacitive effect) is alleviated by inserting normal NMOS transistors in parallel with each of the FATMOS drivers. One of the disadvantages of employing such shunt transistors is that it increased the number of transistors in the latch by 50%: the area taken up by such a latch in an integrated array is hence greater than desired.